IEEE Project in VLSI

VLSI final year ieee project center tirunelvlei

IEEE Project in VLSI 2017 :

Low Power

1. Energy Efficient Reduce and Rank Using Input Adaptive Approximations
2. ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware
3. Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication
4. Adaptive Multibit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication
5. Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers
6. A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption
7. Resource-Efficient SRAM-based Ternary Content Addressable Memory
8. A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission


1. High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA
2. A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging
3. COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits
4. Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding
5. A 2.4–3.6-GHz Wideband Sub-harmonically Injection-Locked PLL with Adaptive Injection Timing Alignment Technique
6. Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm
7. A 65-nm CMOS Constant Current Source with Reduced PVT Variation
8. High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations
9. Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST
10. Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations
11. Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map


1. RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
2. VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant Binary Encoding
3. A Method to Design Single Error Correction Codes with Fast Decoding for a Subset of Critical Bits
4. Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs
5. Efficient Soft Cancelation Decoder Architectures for Polar Codes
6. Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition
7. Efficient Designs of Multiported Memory on FPGA
8. Hybrid LUT Multiplexer FPGA Logic Architectures
9. FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers over GF (2m) and Their Applications in Trinomial Multipliers
10. Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture
11. Energy-Efficient VLSI Realization of Binary64 Division with Redundant Number Systems
12. Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares
13. Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction
14. An FPGA-Based Hardware Accelerator for Traffic Sign Detection
15. Antiwear Leveling Design for SSDs With Hybrid ECC Capability
16. A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy


1. A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding


1. Publicly Verifiable Watermarking for Intellectual Property Protection in FPGA Design
2. Interconnection Allocation between Functional Units and Registers in High-Level Synthesis
3. Multicast-Aware High-Performance Wireless Network-on-Chip Architectures


1. Scalable Device Array for Statistical Characterization of BTI-Related Parameters
2. Write-Amount-Aware Management Policies for STT-RAM Caches
3. Temporarily Fine-Grained Sleep Technique for Near- and Subthreshold Parallel Architectures
4. Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique
5. Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
6. Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template
7. A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures
8. 10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage
9. A Single Channel Split ADC Structure for Digital Background Calibration in Pipelined ADCs
10. Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology
11. A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing
12. Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Non-binary LDPC Codes Over Subfields
13. Variation Resilient Power Sensor with an 80-ns Response Time for Fine-Grained Power Management
14. A 100-mA, 99.11% Current Efficiency, 2-mVppRipple Digitally Controlled LDO with Active Ripple Suppression
15. Delay Analysis for Current Mode Threshold Logic Gate Designs
16. Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications
17. Probability-Driven Multibit Flip-Flop Integration With Clock Gating
18. A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications
19. A 5-Gb/s Digital Clock and Data Recovery Circuit with Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network
20. High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder
21. Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application
22. An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock
23. A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS
24. An All-MOSFET Sub-1-V Voltage Reference With a-51-dB PSR up to 60 MHz
25. Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA
26. Temporarily Fine-Grained Sleep Technique for Near- and Subthreshold Parallel Architectures

VLSI final year ieee project center tirunelvlei

IEEE Project in VLSI 2016 :

1. Enhancing Sensor Pattern Noise via Filtering Distortion Removal
2. A Deterministic Approach to Detect Median Filtering in 1D Data
3. Fast Spectrum Analysis for an OFDR Using the FFT and SCZT Combination Approach
4. Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation
5. Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks
6. Concept, Design, and Implementation of Reconfigurable CORDIC
7. A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta–Sigma Modulator
8. Design Tradeoffs and Challenges in Practical Coherent Optical Transceiver Implementations
9. Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing
10. An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop
11. A High-Throughput Hardware Design of a One-Dimensional SPIHT Algorithm
12. Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic
13. Exploiting Serial Access and Asymmetric Read/Write of Domain WallMemory for Area and Energy-Efficient Digital Signal Processor Design
14. Hybrid Architecture Design for Calculating Variable-Length Fourier Transform
15. Multiple Constant Multiplication Algorithm for High-Speed and Low-Power Design
16. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
17. A reconfigurable block cryptographic processor based on VLIW architecture
18. Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture
19. A Survey of Public-Key Cryptographic Primitives in Wireless Sensor Networks
20. Cost-Effective Design Strategies for Securing Embedded Processors
21. More Efficient Privacy Amplification With Less Random Seeds via Dual Universal Hash Function
22. Effectively Exploiting Parasitic Arrays for Secret Key Sharing
23. Insecure by Design: Protocols for Encrypted Phone Calls
24. Security analysis and enhanced design of a dynamic block cipher
25. An All-Digital Edge Racing True Random Number Generator Robust Against PVT Variations
26. Impact of Propagation on the Vulnerability of Channel-Based Key Establishment
27. A Lightweight Authenticated Communication Scheme for Smart Grid
28. A Security-Enhanced Alignment-Free Fuzzy Vault-Based Fingerprint Cryptosystem Using Pair-Polar Minutiae Structures
29. A Cell-Array-Based Multibiometric Cryptosystem
30. Distance Based Leakage Alignment for Side Channel Attacks
31. Artificial-Noise-Aided Message Authentication Codes With Information-Theoretic Security
32. Iris Recognition Based on Human-Interpretable Features
33. Distributed Secret Sharing Approach With Cheater Prevention Based on QR Code
34. S-box: Six-dimensional compound hyperchaotic map and artificial bee colony algorithm
35. A New Parallel VLSI Architecture for Real-Time Electrical Capacitance Tomography
36. Real-time digital image stabilization based on regional field image gray projection
37. Image-Like 2D Barcodes Using Generalizations of the Kuznetsov–Tsybakov Problem
38. Word-Hunt: A LSB Steganography Method with Low Expected Number of Modifications per Pixel
39. Multiplicative Watermark Decoder in Contourlet Domain Using the Normal Inverse Gaussian Distribution
40. Zero coefficient-aware fast butterfly-based inverse discrete cosine transform algorithm.
41. A Column-Row-Parallel ASIC Architecture for 3-D Portable Medical Ultrasonic Imaging
42. Noise-insensitive and edge-preserving resolution upconversion scheme for digital image based on the spatial general autoregressive model
43. A Low-Power Gateable Vernier Ring Oscillator Time-to-Digital Converter for Biomedical Imaging Applications
44. Combination of hybrid median filter and total variation minimisation for medical X-ray image restoration
45. Efficient, Edge-Aware, Combined Color Quantization and Dithering
46. Image-Based Motion-Tolerant Remote Respiratory Rate Evaluation
47. Content-Based Guided Image Filtering, Weighted Semi-Global Optimization, and Efficient Disparity Refinement for Fast and Accurate Disparity Estimation
48. Edge-Aware BMA Filters
49. Low-light image enhancement for multiaperture and multitap systems
50. A Morphological Mean Filter for Impulse Noise Removal
51. Brain tumour classification using two-tier classifier with adaptive segmentation technique
52. Lossless Frame Memory Compression Using Pixel-Grain Prediction and Dynamic Order Entropy Coding
53. Block-based discrete wavelet transform-singular value Decomposition image watermarking scheme using human visual system characteristics

VLSI final year ieee project center tirunelvlei

IEEE Project in VLSI 2015 :

1. Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path
2. Key Updating for Leakage Resiliency With Application to AES Modes of Operation
3. Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology
4. FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic
5. Logic-in-Memory With a Nonvolatile Programmable Metallization Cell
6. Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures
7. Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
8. Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
9. Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories
10. An Optimized Modified Booth Recoder for Efficient Design of the Add- Multiply Operator
11. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications